The Need

Analog-to-digital conversion is carried out in a variety of computer and communications applications. Different types of analog-to-digital converters (ADCs) have been developed to convert an analog signal, such as voltage, to a digital signal with a value that corresponds to the magnitude of the analog signal. Current ADCs rely on analog components that face difficulties in scaling to nanometer feature sizes and are incompatible with low voltage devices. There is a need for smaller and faster ADCs that maintain a high level of accuracy.

The Technology

Researchers at The Ohio State University, led by Dr. YiQiao Lin, developed a novel phase-based sigma-delta ADC that employs clock time delay as the intermediary to convert analog voltage signal to digital bits. Two architectures were employed to demonstrate this ADC. Since the architectures are predominantly digital, it can be a highly desirable solution for low power nano-scale device design. These models offer both reference jitter shaping and quantization noise shaping:

1. Uses a Delay-Locked-Loop mechanism that uses a phase quantizer. ADC achieved 50.5 dB SNDR, or 8.09 bits resolution for a 10 MHz signal bandwidth.
2. Adopts a VCDL/DCDL combination playing the roles of ADC/DAC in the conventional modulator in the phase domain. The new modulator achieves a 57.8 dB SNR, or a 9.28 bit over a 10 MHz bandwidth.

Benefits/Advantages

• Time-based ADC, as opposed to the more conventional amplitude based, allows this ADC to circumvent limited voltage signal swings
• Can digitally scale to nanometer feature sizes due to the predomination of digital circuits
• Avoids relying on analog components
• Can use low voltage devices
• Low power
• Small die size