The Need
Cyclic redundancy checks (CRC) are utilized in digital communication and storage systems for error detection. Current CRC encoding and decoding methods in digital communication and storage systems are complex and require a high gate count, leading to inefficiencies in hardware design. There is a need for a simpler, more efficient solution that reduces the complexity and gate count while maintaining high performance and reliability.

The Technology
This technology introduces a novel design for parallel Linear Feedback Shift Registers (LFSRs) used in CRC encoding and decoding. By optimizing the feedback matrix multiplication, the design significantly reduces the gate count and simplifies the hardware. This is achieved by interpreting the input data polynomial differently, allowing for a more efficient feedback matrix construction.

Commercial Applications
• Telecommunications: For improving error detection in data transmission.
• Data Storage: To enhance data integrity and reliability in storage systems.
• Networking Equipment: For better error detection and correction in networking hardware.
• Consumer Electronics: To ensure reliable data processing in devices like smartphones and tablets.
• Automotive: For use in advanced driver-assistance systems and other in-vehicle communication systems.

Benefits/Advantages
• Reduces gate count by 18-53%, leading to simpler and cheaper hardware.
• Shortens the critical path, enhancing system performance.
• Meets IEEE standards while offering improved efficiency.
• Simplifies the design, making it easier to implement and adjust.
• Suitable for high-speed data processing applications, ensuring reliable error detection and correction.